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Restructuring WSI hexagonal processor arrays

Fault-tolerant approaches have been widcly em­ ployed to improve the yield of ULSI and WSI processor arrays. In this paper, we propose a host-driven reconfiguration scheme, called HEX-REPAIR, for hexagonal processor arrays charac­ terized by a large number of relatively simple cells. Such arrays have heen shown to be the most efficient for many digital signal processing applications, such as ma...

WSI GRIS Compression of Discrete Multiresolution Models

VLSI, MCM, and WSI: A Design Comparison

Optimizing Real-Time Fault Tolerance Design in WSI

VLSI/WSI Designs for Folded Cube-Connected Cycles Architectures

This paper presents VLSI/WSI designs for a recently introduced parallel architecture known as the folded cube-connected cycles ( F C C C ) . We first discuss two layouts for the FCCC, in which there is no component redundancy. Then we incorporate redundancy, and present locally and globally reconfigurable FCCCs. We also discuss the design of universal building blocks for the construction of fau...